Semiconductor chips are formed on a wafer. After fabrication processes are completed, the wafer is diced by cutting the wafer along kerfs resulting in the singulation of the chips, e.g., separate chips. The dicing processes is a physical process which induces stress into the chips. These stresses result in stress cracks forming through the semiconductor chip structure, which can degrade or even destroy the functionality of the chip, itself. For example, cracks typically form along interfaces between metal structures and dielectric materials, with some portions of the semiconductor structures particularly susceptible to crack propagation.
To avoid such stress cracks designers use guard ring structures to surround the active region of the chip. However, after the chip is fully fabricated, these guard ring structures can prevent the use of contacts to the outside for testing. Thus, in order to have contacts extending from the inner portion of the chip, it is necessary to go around the guard ring structure. This may result in a propagation path or moisture ingress into the chip.
Moisture greatly impacts integrated circuit reliability and performance. For example, moisture ingression during chip operational lifetime increases chip functional failure, particularly as technology scales. For example, capacitance shift due to moisture ingression (k value increases) will negatively impact performance (e.g., RC delay). Moreover, low-k interlevel dielectric (ILD) TDDB failure times, voltage acceleration, and temperature acceleration all degrade significantly with the ingress of moisture within an integrated circuit. These failures can become even more pronounced in integrated circuit designs in smaller technology nodes which do not take into consideration an increased likelihood of chip edge seal breakage due to high temperature swings or high mechanical stress generated by low-k ILD integration and high density circuit layouts.